The present invention relates to a ferroelectric memory including a capacitive element in which a ferroelectric film is used as a capacitor insulative film, and a method for manufacturing the same.
It is most important for realizing a ferroelectric memory to develop a device structure and a manufacturing method therefor that allow for integration without deteriorating the characteristics of the capacitive element.
Particularly, since a ferroelectric film is a layered oxide film having oxygen atoms, it is easily reduced in a hydrogen atmosphere, thereby leading to deterioration of the characteristics of the ferroelectric film such as a reduction in polarizability or voltage endurance. Meanwhile, semiconductor memory manufacturing often employs integration processes that are performed in a hydrogen atmosphere or a reducing atmosphere. Therefore, in cases where a ferroelectric film is used as a capacitor insulative film of a capacitive element, it is important to construct a process that is highly resistant to reduction.
In view of this, various measures have been taken in the prior art to prevent the characteristics of a capacitive element from deteriorating during the manufacture of a ferroelectric memory, e.g., reducing the amount of hydrogen to be generated or suppressing the reducing atmosphere in subsequent steps after the formation of the capacitive element, or covering a capacitive element section by an insulative hydrogen barrier film.
A ferroelectric memory according to a first conventional example will now be described with reference to FIG. 36.
As illustrated in FIG. 36, a device isolation region 11 having an STI (shallow trench isolation) structure is formed in a surface portion of a semiconductor substrate 10, and a low-concentration impurity diffusion layer 12 to be the lower layer and a high-concentration impurity diffusion layer 13 to be the upper layer are formed in a surface portion of each region of the semiconductor substrate 10 surrounded by the device isolation region 11. The low-concentration impurity diffusion layer 12 and the high-concentration impurity diffusion layer 13 are to be a source region or a drain region of a transistor forming a part of a memory cell (hereinafter referred to as a “memory cell transistor”).
Moreover, a first interlayer insulating film 14 is formed on the semiconductor substrate 10, on which the memory cell transistor has been formed, and a first plug 15 made of tungsten and connected to the high-concentration impurity diffusion layer 13 is formed through the first interlayer insulating film 14. A capacitor lower electrode 16 is formed on the first interlayer insulating film 14. The capacitor lower electrode 16 is made of a conductive film having an oxygen barrier property and covers the upper surface of the first plug 15. An insulative film 17 is formed in each region between adjacent capacitor lower electrodes 16 so that the upper surface thereof is coplanar with the upper surface of the capacitor lower electrode 16.
Moreover, a capacitor insulative film 18 made of a ferroelectric film is formed on the capacitor lower electrode 16 so as to cover the upper surface of the capacitor lower electrode 16, and a capacitor upper electrode 19 made of Pt (platinum) is formed on the capacitor insulative film 18 so as to cover the upper surface of the capacitor insulative film 18. Thus, a capacitive element, including the capacitor lower electrode 16, the capacitor insulative film 18 and the capacitor upper electrode 19, is formed.
Moreover, a second interlayer insulating film 20 is formed on the first interlayer insulating film 14 including the capacitive element, and a second plug 21 made of tungsten and connected to the capacitor upper electrode 19 is formed through the second interlayer insulating film 20.
Moreover, a wiring 22 made of aluminum, or the like, and connected to the second plug 21 is formed on the second interlayer insulating film 20, and a third interlayer insulating film 23 is formed on the second interlayer insulating film 20 including the wiring 22. A third plug 24 connected to the wiring 22 is formed through the third interlayer insulating film 23.
Although not shown, a further interlayer insulating film, a further wiring, a surface protection film, etc., are formed on the third interlayer insulating film 23 to complete the ferroelectric memory.
With the device structure of the ferroelectric memory according to the first conventional example, integration can be realized.
A ferroelectric memory according to a second conventional example will now be described with reference to FIG. 37.
The ferroelectric memory of the second conventional example differs from that of the first conventional example in that the capacitive element section, including the capacitor lower electrode 16, the capacitor insulative film 18 and the capacitor upper electrode 19, is covered by an insulative hydrogen barrier film 25, as illustrated in FIG. 37 (see Japanese Laid-Open Patent Publication No. 11-121704). Note that the insulative hydrogen barrier film 25 may be an SiN film, an SiON film, a TiO2 film, TaOx (where x>0) film, or the like.
With the device structure of the ferroelectric memory according to the second conventional example, it is possible to prevent the characteristics of the capacitive element from deteriorating during the manufacturing process.
With the first conventional example, however, a portion of the capacitor upper electrode 19 is exposed upon formation of a contact hole through the second interlayer insulating film 20, in which the second plug 21 connecting the capacitor upper electrode 19 and the wiring 22 to each other is to be formed. As a result, hydrogen included in an etching gas or a resist is absorbed by the capacitor upper electrode 19, i.e., a Pt film. Also when a WF6 (tungsten hexafluoride) gas is used with another gas such as a hydrogen gas or a silane gas (both of which reduce the WF6 gas to produce W (tungsten)) in order to form the second plug 21 embedded in the contact hole, hydrogen (including hydrogen that is produced through decomposition of a silane gas) is absorbed by the Pt film of the capacitor upper electrode 19. Then, hydrogen absorbed by the Pt film is later discharged from the Pt film as highly active hydrogen (hereinafter referred to as “active hydrogen”) in subsequent steps. In other words, the Pt film has a catalytic function. As a result, a portion of the ferroelectric film of the capacitor insulative film 18 in the vicinity of the second plug 21 is reduced, and deprived of oxygen, by the active hydrogen produced by the catalytic function of the Pt film, thereby deteriorating the characteristics of the ferroelectric film, which may lead to a bit failure, etc., in the ferroelectric memory.
In the second conventional example, although the capacitive element section is covered by the insulative hydrogen barrier film 25, as illustrated in FIG. 37, a portion of the capacitor upper electrode 19 will still be exposed upon formation of a lower part of the contact hole through the insulative hydrogen barrier film 25, in which the second plug 21 is to be formed. Therefore, problems as those encountered by the first conventional example are likely to occur.
Even if a Pt film, which is advantageous for the crystal growth of a ferroelectric film (typically performed after the formation of the capacitor upper electrode 19), is not used in the first or second conventional example, it is difficult to completely prevent a portion of the ferroelectric film of the capacitor insulative film 18 in the vicinity of the second plug 21 from being damaged by hydrogen.